【工作筆記】Timing violation－異想，天開

Solving Setup violation

1. At first check whether the path is a valid path means whether this path will be exercised in your chip or it is a false path.
2. Check with the design specification whether the specified path could operate as a multicycle path rather than a single cycle path.
Assume it is a valid path.
1. Now check the wireload models used .
2. Check the loading of the high fanout nets.
3. group_path -from startpoint -to end point -weightage 100 and ask the tool to concentrate more on the specific paths.
4. use various compile options try with various switches.
5. Use designware components if you have logic similar to adders/multipliers .
6. Use compile_ultra options to speed up the paths which uses different algorithms for optimizations.
7. Use the flip-flops which has lesser setup time.
8. In case if the paths or of cross clock domains check whether the path is of synchronization logic, which usually is a false path as we have synchronizers in these paths.
9. In case you could use low Vt libraries which has faster delays can be used for specific paths to close on timing.check these options whether dual Vt flow is allowed .
10. check whether these paths could be solved in timing by using useful-skew concept after place and route by optimal clocktree building.

Solving hold violation

1. By adding more delay in the data path, by adding buffers.